Arm has unveiled its semi-custom Neoverse CSS N4 server platform (code-named Ranger). The validated compute subsystem packs up to 128 cores per die on TSMC N3P and slashes hyperscale CPU time-to-marke…
The Compute Subsystems (CSS) N4 Ranger platform is engineered with Armv9.3-A cores optimized for high-density cloud throughput and inference. Each core features SVE2 vector units and SME2 (Scalable Matrix Extension) to accelerate transformer operations directly on the CPU.
Each die integrates up to 128 compute cores with up to 128MB SLC cache and 8-channel DDR5-6400 or LPDDR5X ECC memory.
• Process Node: WAS 5nm (TSMC N5) in N2 : NOW 3nm (TSMC N3P) in N4 Ranger
• Max Cores per Die: WAS 64 cores : NOW 128 cores per die (+100% density)
• PCIe Interface: WAS PCIe 5.0 (32 GT/s) : NOW PCIe 6.0 with PAM4 (64 GT/s)
• AI Coherency: WAS CXL 2.0 : NOW CXL 3.1 with memory pooling
• Perf / Watt: WAS Baseline : NOW +25% compute per watt
• Time-to-Silicon: WAS 13-18 months : NOW 9 months tape-out to silicon
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Arm has unveiled its semi-custom Neoverse CSS N4 server platform (code-named Ranger). The validated compute subsystem packs up to 128 cores per die on TSMC N3P and slashes hyperscale CPU time-to-market from two years down to 9 months.
This development reshapes competitive dynamics in the sector.
Regulatory frameworks and infrastructure readiness remain critical.
Mainstream adoption expected within 3–5 years.